Integrated circuit (IC) devices are prone to electrostatic discharge (ESD) events, whereby external contacts of the IC devices are subjected to large electrical charges (positive or negative). Functional circuitry within an IC device is required to be protected from electrical currents created by such large electrical charges at the external contacts of the IC devices, which can cause erroneous behavior within the functional circuitry and even permanently damage the functional circuitry due to the magnitude of the electrical currents that can be generated by ESD events.
To protect the functional circuitry of an IC device from ESD events, it is known to provide susceptible external contacts of the IC device with ESD protection structures. Conventional ESD protection structures typically include thyristor structures (i.e. P-N-P-N semiconductor structures) coupled between an external contact to be protected, such as an input/output (I/O) contact of the IC device, and a power supply contact (e.g. ground or Vss) to which ESD currents are to be shunted.
Many applications require bidirectional ESD protection to be provided for at least some of the external contacts of an IC device. Conventionally, a high voltage bidirectional N-P-N ESD protection structure is used to provide the bidirectional ESD protection. FIG. 1 schematically illustrates a conventional 2-stack bidirectional NPN ESD protection structure formed within a semiconductor substrate.
The footprint of ESD protection structures at the external contacts of IC devices is a significant limiting factor in the minimum die size that can be achieved. To reduce the footprint of the ESD protection structures, an area-efficient version of the conventional bidirectional NPN ESD protection structure illustrated in FIG. 1 was developed. FIG. 2 schematically illustrates such an area-efficient version of the 2-stack bidirectional NPN ESD protection structure of FIG. 1.
A problem with the known area-efficient version of the bidirectional NPN ESD protection structure illustrated in FIG. 2 is that it suffers from a lower holding voltage (Vh) than regular bidirectional NPN ESD protection structure illustrated in FIG. 1, and is thus more susceptible to latch-up conditions.
FIG. 3 illustrates a typical TLP (transmission line pulse) curve of ESD protection structures showing the triggering point (Vt1, It1), first snapback point (Vh and Ih), and second snapback point (Vt2, It2). The current value It2 at the second snapback point defines the current capability of the device before it is thermally damaged by power. The voltage value Vt1 at the triggering point is usually closely correlated to the breakdown voltage for breakdown-triggered devices such as bidirectional NPN devices.
The conventional approach to increasing the holding voltage of a bidirectional NPN ESD protection structure is to enlarge the current path. However, enlarging the current path increases the footprint of the bidirectional NPN ESD protection structure. Accordingly, there is a need for an area-efficient bidirectional NPN ESD protection structure that does not suffer from a reduced holding voltage.